Over 10 years we help companies reach their financial and branding goals. Engitech is a values-driven technology agency dedicated.

Gallery

Contacts

411 University St, Seattle, USA

engitech@oceanthemes.net

+1 -800-456-478-23

PCB Manufacturing
High-Speed PCB

Four Key Points in High-Speed PCB Design

When designing high-speed PCBs, process variations and other factors can significantly impact actual impedance. Automated design tools may not always detect these subtleties, making proactive, defensive design essential. Here’s how to address common challenges in high-speed PCB design.

1. Layer Stack-Up Configuration

A well-configured layer stack-up is foundational for signal integrity (SI) and electromagnetic compatibility (EMC). Ideally, there should be at least one continuous plane for impedance control and signal quality. EMC consultants may also recommend ground fills on outer layers to manage electromagnetic radiation.

However, this setup can sometimes lead to transient currents, especially if power and ground planes are too far apart, causing increased current loops and noise. Key concerns include:

  • Crosstalk: Greater spacing between signal layers increases crosstalk.
  • Loop Currents: Increased loop area can worsen EMC.
  • Impedance Control: Greater distances reduce control over impedance.

To mitigate these, the main power and ground planes should be adjacent and central within the layer stack.

High-Speed PCB

2. Controlling Characteristic Impedance

A stable stack-up effectively manages impedance by creating predictable transmission lines. Some high-speed devices, like CMOS, operate around 70Ω, while TTL devices range from 80Ω to 100Ω. Impedance must be controlled carefully, especially when signal layers are adjacent to other conductors, which could cause variations.

However, impedance control tools might not detect certain layers or copper areas that impact impedance. For example, adjacent metal layers could act as unreliable ground planes, increasing EMI. Proper layer configuration and consistent routing practices help maintain impedance.

3. Delay Management

During simulation, both component capacitance and package effects need consideration. Factors like distributed capacitance and non-parallel traces can disrupt the intended delay, which varies based on production tolerances and stack-up configurations. When using signal layers with a nearby ground plane, carefully manage delay calculations by accounting for capacitance variations, especially in dense PCB layouts.

4. Addressing EMC Issues

Various design details impact EMC, including:

  • Layer Slots: These can act as antennas, especially if placed near metal containers.
  • Inductive Components: Placing inductors too close may create transformers and lead to unwanted signals.
  • Incomplete Ground Layers: Low inner-layer impedance causes high transient currents.

Defensive design strategies, such as correct stack-up and routing, are crucial. Key aspects like layer alignment and controlled via placement provide a good foundation for EMC control.

KKPCB conducts research on special processing technologies such as ordinary double-sided boards, thick copper circuit boards, high-frequency circuit boards, HDI circuit boards, rigid-flexible circuit boards, FPC flexible boards, buried blind hole circuit boards, and IC carrier boards. Provides PCB design, PCB layout, PCB prototyping and PCB assembly services.

Author

kkpcb-admin

Leave a comment

Your email address will not be published. Required fields are marked *