There are many ways to solve the EMI problem. Modern EMI suppression methods include: using EMI suppression coatings, selecting appropriate EMI suppression components and EMI simulation design, etc. This article starts with the most basic PCB layout and discusses the role and design techniques of PCB layer stacking in controlling EMI radiation.

Power Bus

Reasonably placing a capacitor of appropriate capacity near the IC’s power pin can make the IC’s output voltage jump faster. However, the problem does not end there. Due to the finite frequency response of the capacitor, the capacitor cannot generate the harmonic power required to cleanly drive the IC output over the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop across the inductor of the decoupling path. These transient voltages are the main source of common-mode EMI interference. How should we solve these problems?

As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of an excellent power layer should be small, so that the transient signal synthesized by the inductance is also small, thereby reducing common-mode EMI.

Of course, the connection from the power layer to the IC power pin must be as short as possible. Because the rising edge of the digital signal is getting faster and faster, it is best to connect directly to the pad where the IC power pin is located. This needs to be discussed separately.

In order to control common-mode EMI, the power plane must aid in decoupling and have sufficiently low inductance. This power plane must be paired with a reasonably well-designed power plane. One might ask, how good is good? The answer depends on the layering of the power supply, the materials between the layers, and the operating frequency (i.e., a function of the IC rise time). Typically, the spacing of the power layer is 6mil, and the interlayer is made of FR4 material. The equivalent capacitance of the power layer per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many devices with a rise time of 100 to 300ps, but according to the current IC development speed, devices with a rise time in the range of 100 to 300ps will account for a high proportion. For circuits with 100 to 300ps rise time, 3mil layer spacing will no longer be suitable for most applications. At that time, it will be necessary to adopt layering technology with a layer spacing of less than 1 mil and replace the FR4 dielectric material with a material with a very high dielectric constant . Today, ceramics and ceramic-coated plastics can meet the design requirements of circuits with rise times from 100 to 300ps.

Although new materials and approaches may be adopted in the future, for today’s common 1 to 3ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials, it is usually sufficient to handle the high end harmonics and keep the transients low enough, that is , common mode EMI can be reduced very low. The PCB layer stackup design examples given in this article will assume a layer spacing of 3 to 6 mils.

Electromagnetic shielding

From the perspective of signal routing, a good layering strategy should be to place all signal routing on one or several layers, with these layers next to the power layer or ground layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the “layering” strategy.

PCB Stack-up

What stacking strategy helps shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer, with single voltage or multiple voltages distributed in different parts of the same layer. The case of multiple power planes is discussed later.

4-layer board

There are several potential problems with 4-layer board design. First, for a traditional 62mil thick 4-layer board, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the spacing between the power layer and the ground layer is still too large.

If cost requirements are the first priority, consider the following two alternatives to traditional 4-layer boards. Both solutions can improve the performance of EMI suppression, but are only suitable when the component density on the board is low enough and there is sufficient area around the components to place the required power copper layer.

The first is the preferred solution, where the outer layers of the PCB are all ground layers, and the two middle layers are signal/power layers. The power supply on the signal layer is routed with a wide line, which can make the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From the perspective of EMI control, this is the best 4-layer PCB structure available. The second solution uses power and ground on the outer layers, and signals on the middle two layers. This solution is less improved than the traditional 4-layer board, and the inter-layer impedance is as poor as the traditional 4-layer board.

If you want to control the trace impedance, the above stacking schemes must be very careful to arrange the traces under the power and ground copper islands. In addition, the copper islands on the power or ground layer should be interconnected as much as possible to ensure DC and low-frequency connectivity.

6-layer board

If the density of components on a 4-layer board is relatively high, a 6-layer board is preferred. However, some stacking schemes in a 6-layer board design do not provide adequate shielding of electromagnetic fields and have little effect on reducing transient signals on the power bus. Two examples are discussed below.

In the first example, the power supply and ground are placed on the 2nd and 5th layers respectively. Due to the high impedance of the power supply copper, it is very unfavorable for controlling common mode EMI radiation. However, from the perspective of signal impedance control, this method is very correct.

The second example places the power supply and ground on the 3rd and 4th layers respectively. This design solves the problem of power supply copper impedance. Due to the poor electromagnetic shielding performance of the 1st and 6th layers, differential mode EMI increases. If the number of signal lines on the two outer layers is minimized and the trace length is short (shorter than 1/20 of the highest harmonic wavelength of the signal), this design can solve the differential mode EMI problem. Filling the component-free and trace-free areas on the outer layer with copper and grounding the copper-clad area (every 1/20 wavelength is an interval) will suppress differential mode EMI particularly well. As mentioned before, connect the copper area to the internal ground layer at multiple points.

A general high-performance 6-layer board design generally places the 1st and 6th layers as ground layers, and the 3rd and 4th layers carry power and ground. Since there are two centrally located dual microstrip signal line layers between the power layer and the ground layer, the EMI suppression capability is excellent. The disadvantage of this design is that there are only two routing layers. As mentioned earlier, if the outer traces are short and copper is laid in the trace-free area, the same stack can be achieved with a traditional 6-layer board.

Another 6-layer board layout is signal, ground, signal, power, ground, signal, which can achieve the environment required for advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power layer and ground layer are paired. Obviously, the disadvantage is that the stacking of the layers is unbalanced.

This often creates problems in manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. After filling with copper, if the copper density of the third layer is close to the power layer or ground layer, the board can be loosely regarded as a structurally balanced circuit board. . The copper-filled area must be connected to power or ground. The distance between connecting vias is still 1/20 wavelength, they don’t necessarily have to connect everywhere, but ideally they should.

10-layer board

Since the insulation isolation layer between multi-layer boards is very thin, the impedance between the layers of a 10- or 12-layer circuit board is very low. As long as there are no problems with layering and stacking, excellent signal integrity is fully expected. It is more difficult to process and manufacture 12-layer boards with a thickness of 62 mil, and there are not many manufacturers that can process 12-layer boards.

Since there is always an insulating layer between the signal layer and the loop layer, allocating the middle 6 layers for signal lines in a 10-layer board design is not the best solution. Also, it is important to have the signal layer adjacent to the loop layer, i.e. the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.

This design provides a good path for signal current and its loop current. The appropriate routing strategy is that layer 1 should be routed in the X direction, layer 3 should be routed in the Y direction, layer 4 should be routed in the X direction, and so on. Looking at the wiring intuitively, layer 1 and layer 3 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are the last pair of layered combinations. When the wiring direction needs to be changed, the signal lines on the first layer should be moved to the third layer through “vias” before changing the direction. In practice, this may not always be possible, but as a design concept it should be adhered to as much as possible.

Similarly, when the signal routing direction changes, it should be from the 8th and 10th layers or from the 4th to the 7th layer through vias. Routing this way ensures the tightest coupling between the forward path of the signal and the return path. For example, if the signal is routed on layer 1 and the loop is routed on layer 2 and only on layer 2, then even if the signal on layer 1 is transferred to layer 3 through a “via”, its The loop is still on layer 2, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.

What if the actual wiring is not like this? For example, the signal line on the 1st layer passes through the via hole to the 10th layer. At this time, the loop signal has to find the ground plane from the 9th layer, and the loop current has to find the nearest ground via hole (such as The ground pin of a component such as a resistor or capacitor). You’re really lucky if you happen to have such a via nearby. If there are no such close vias available, the inductance will become larger, the capacitance will be reduced, and EMI will definitely increase.

When the signal line must leave the current pair of wiring layers to other wiring layers through via holes, ground vias should be placed nearby the via holes, so that the loop signal can smoothly return to the appropriate ground layer. For the layered combination of layer 4 and layer 7, the signal loop will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitive coupling between the power layer and ground layer is good and the signal is easily transmitted.

Multi-power layer design

If two power layers of the same voltage source need to output large currents, the circuit board should be laid out into two sets of power layers and ground layers. In this case, an insulating layer is placed between each pair of power layers and ground layers. In this way, we get two pairs of power buses with equal impedance that divide the current equally as we expect. If the stacking of power layers causes unequal impedance, the current division will be uneven, the transient voltage will be much larger, and EMI will increase dramatically.

If there are multiple power supply voltages with different values ​​on the circuit board, multiple power supply layers are required accordingly. Remember to create paired power and ground layers for different power supplies. In both cases, when determining the location of paired power and ground layers on the circuit board, keep in mind the manufacturer’s requirements for balanced structures.

Summarize

Given that most engineers design circuit boards that are 62 mil thick, traditional printed circuit boards without blind or buried vias, this article’s discussion of circuit board layering and stacking is limited to this. For circuit boards with greatly different thicknesses, the layering scheme recommended in this article may not be ideal. In addition, the processing process of circuit boards with blind holes or buried holes is different, and the layering method in this article is not applicable.

In circuit board design, the thickness, via process and number of circuit board layers are not the key to solving the problem. Excellent layer stacking is the key to ensure bypass and decoupling of the power bus, minimize transient voltage on the power layer or ground layer, and shield the electromagnetic field of the signal and power supply. Ideally, there should be an insulating isolation layer between the signal routing layer and its loop ground layer, and the spacing between paired layers (or more than one pair) should be as small as possible. Based on these basic concepts and principles, a circuit board that always meets the design requirements can be designed. Now that the rise time of ICs is very short and will be shorter, the technology discussed in this article is essential to solving the EMI shielding problem

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